
		AREA	|ARM$$code|,CODE,READONLY

		IMPORT	Pico

		EXPORT	TileNorm16
		EXPORT	TileFlip16
		EXPORT	TileNorm32
		EXPORT	TileFlip32

		; horizontal doubling

		EXPORT	TileNorm16_2
		EXPORT	TileFlip16_2
		EXPORT	TileNorm32_2
		EXPORT	TileFlip32_2


Pico_vram	*	&10000

;-----------------------------------------------------
;
; Unity scaling routines
;
;-----------------------------------------------------

TileFlip16	LDR	ip,=Pico
		ADD	ip,ip,#Pico_vram
		LDR	a4,[ip,a2,LSL #1]
		PLD	[ip,#64]

		TEQ	a4,#0
		MOVEQ	pc,lr

		ANDS	a2,a4,#&000F0000
		AND	ip,a4,#&00F00000
		LDRNE	a2,[a3,a2,LSR #14]
		LDR	ip,[a3,ip,LSR #18]
		STRNEH	a2,[a1,#0]
		TST	a4,#&00F00000
		STRNEH	ip,[a1,#2]

		ANDS	a2,a4,#&0F000000
		AND	ip,a4,#&F0000000
		LDRNE	a2,[a3,a2,LSR #22]
		LDR	ip,[a3,ip,LSR #26]
		STRNEH	a2,[a1,#4]

		TST	a4,#&F0000000
		STRNEH	ip,[a1,#6]

		ANDS	a2,a4,#&0000000F
		AND	ip,a4,#&000000F0
		LDRNE	a2,[a3,a2,LSL #2]
		LDR	ip,[a3,ip,LSR #2]
		STRNEH	a2,[a1,#8]

		TST	a4,#&000000F0
		STRNEH	ip,[a1,#10]

		ANDS	a2,a4,#&00000F00
		AND	ip,a4,#&0000F000
		LDRNE	a2,[a3,a2,LSR #6]
		LDR	ip,[a3,ip,LSR #10]
		STRNEH	a2,[a1,#12]
		TST	a4,#&0000F000
		STRNEH	ip,[a1,#14]

		MOV	a1,#0
		MOV	pc,lr


TileNorm16	LDR	ip,=Pico
		ADD	ip,ip,#Pico_vram
		LDR	a4,[ip,a2,LSL #1]
		PLD	[ip,#64]

		TEQ	a4,#0
		MOVEQ	pc,lr

		ANDS	a2,a4,#&F000
		AND	ip,a4,#&0F00
		LDRNE	a2,[a3,a2,LSR #10]
		LDR	ip,[a3,ip,LSR #6]
		STRNEH	a2,[a1,#0]
		TST	a4,#&0F00
		STRNEH	ip,[a1,#2]

		ANDS	a2,a4,#&00F0
		AND	ip,a4,#&000F
		LDRNE	a2,[a3,a2,LSR #2]
		LDR	ip,[a3,ip,LSL #2]
		STRNEH	a2,[a1,#4]
		TST	a4,#&000F
		STRNEH	ip,[a1,#6]

		ANDS	a2,a4,#&F0000000
		AND	ip,a4,#&0F000000
		LDRNE	a2,[a3,a2,LSR #26]
		LDR	ip,[a3,ip,LSR #22]
		STRNEH	a2,[a1,#8]
		TST	a4,#&0F000000
		STRNEH	ip,[a1,#10]

		ANDS	a2,a4,#&00F00000
		AND	ip,a4,#&000F0000
		LDRNE	a2,[a3,a2,LSR #18]
		LDR	ip,[a3,ip,LSR #14]
		STRNEH	a2,[a1,#12]

		TST	a4,#&000F0000
		STRNEH	ip,[a1,#14]

		MOV	a1,#0
		MOV	pc,lr


TileFlip32	LDR	ip,=Pico
		ADD	ip,ip,#Pico_vram
		LDR	a4,[ip,a2,LSL #1]
		PLD	[ip,#64]

		TEQ	a4,#0
		MOVEQ	pc,lr

		ANDS	a2,a4,#&000F0000
		AND	ip,a4,#&00F00000
		LDRNE	a2,[a3,a2,LSR #14]
		LDR	ip,[a3,ip,LSR #18]
		STRNE	a2,[a1,#0]
		TST	a4,#&00F00000
		STRNE	ip,[a1,#4]

		ANDS	a2,a4,#&0F000000
		AND	ip,a4,#&F0000000
		LDRNE	a2,[a3,a2,LSR #22]
		LDR	ip,[a3,ip,LSR #26]
		STRNE	a2,[a1,#8]
		TST	a4,#&F0000000
		STRNE	ip,[a1,#12]

		ANDS	a2,a4,#&0000000F
		AND	ip,a4,#&000000F0
		LDRNE	a2,[a3,a2,LSL #2]
		LDR	ip,[a3,ip,LSR #2]
		STRNE	a2,[a1,#16]
		TST	a4,#&000000F0
		STRNE	ip,[a1,#20]

		ANDS	a2,a4,#&00000F00
		AND	ip,a4,#&0000F000
		LDRNE	a2,[a3,a2,LSR #6]
		LDR	ip,[a3,ip,LSR #10]
		STRNE	a2,[a1,#24]
		TST	a4,#&0000F000
		STRNE	ip,[a1,#28]

		MOV	a1,#0
		MOV	pc,lr


TileNorm32	LDR	ip,=Pico
		ADD	ip,ip,#Pico_vram
		LDR	a4,[ip,a2,LSL #1]
		PLD	[ip,#64]

		TEQ	a4,#0
		MOVEQ	pc,lr

		ANDS	a2,a4,#&F000
		AND	ip,a4,#&0F00
		LDRNE	a2,[a3,a2,LSR #10]
		LDR	ip,[a3,ip,LSR #6]
		STRNE	a2,[a1,#0]
		TST	a4,#&0F00
		STRNE	ip,[a1,#4]

		ANDS	a2,a4,#&00F0
		AND	ip,a4,#&000F
		LDRNE	a2,[a3,a2,LSR #2]
		LDR	ip,[a3,ip,LSL #2]
		STRNE	a2,[a1,#8]
		TST	a4,#&000F
		STRNE	ip,[a1,#12]

		ANDS	a2,a4,#&F0000000
		AND	ip,a4,#&0F000000
		LDRNE	a2,[a3,a2,LSR #26]
		LDR	ip,[a3,ip,LSR #22]
		STRNE	a2,[a1,#16]
		TST	a4,#&0F000000
		STRNE	ip,[a1,#20]

		ANDS	a2,a4,#&00F00000
		AND	ip,a4,#&000F0000
		LDRNE	a2,[a3,a2,LSR #18]
		LDR	ip,[a3,ip,LSR #14]
		STRNE	a2,[a1,#24]
		TST	a4,#&000F0000
		STRNE	ip,[a1,#28]

		MOV	a1,#0
		MOV	pc,lr


;-----------------------------------------------------
;
; Horizontal pixel doubling routines
;
;-----------------------------------------------------

TileFlip16_2	LDR	ip,=Pico
		ADD	ip,ip,#Pico_vram
		LDR	a4,[ip,a2,LSL #1]
		PLD	[ip,#64]

		TEQ	a4,#0
		MOVEQ	pc,lr

		ANDS	a2,a4,#&000F0000
		AND	ip,a4,#&00F00000
		LDRNE	a2,[a3,a2,LSR #14]
		LDR	ip,[a3,ip,LSR #18]
		STRNEH	a2,[a1,#0]
		STRNEH	a2,[a1,#2]
		TST	a4,#&00F00000
		STRNEH	ip,[a1,#4]
		STRNEH	ip,[a1,#6]

		ANDS	a2,a4,#&0F000000
		AND	ip,a4,#&F0000000
		LDRNE	a2,[a3,a2,LSR #22]
		LDR	ip,[a3,ip,LSR #26]
		STRNEH	a2,[a1,#8]
		STRNEH	a2,[a1,#10]
		TST	a4,#&F0000000
		STRNEH	ip,[a1,#12]
		STRNEH	ip,[a1,#14]

		ANDS	a2,a4,#&0000000F
		AND	ip,a4,#&000000F0
		LDRNE	a2,[a3,a2,LSL #2]
		LDR	ip,[a3,ip,LSR #2]
		STRNEH	a2,[a1,#16]
		STRNEH	a2,[a1,#18]
		TST	a4,#&000000F0
		STRNEH	ip,[a1,#20]
		STRNEH	ip,[a1,#22]

		ANDS	a2,a4,#&00000F00
		AND	ip,a4,#&0000F000
		LDRNE	a2,[a3,a2,LSR #6]
		LDR	ip,[a3,ip,LSR #10]
		STRNEH	a2,[a1,#24]
		STRNEH	a2,[a1,#26]
		TST	a4,#&0000F000
		STRNEH	ip,[a1,#28]
		STRNEH	ip,[a1,#30]

		MOV	a1,#0
		MOV	pc,lr


TileNorm16_2	LDR	ip,=Pico
		ADD	ip,ip,#Pico_vram
		LDR	a4,[ip,a2,LSL #1]
		PLD	[ip,#64]

		TEQ	a4,#0
		MOVEQ	pc,lr

		ANDS	a2,a4,#&F000
		AND	ip,a4,#&0F00
		LDRNE	a2,[a3,a2,LSR #10]
		LDR	ip,[a3,ip,LSR #6]
		STRNEH	a2,[a1,#0]
		STRNEH	a2,[a1,#2]
		TST	a4,#&0F00
		STRNEH	ip,[a1,#4]
		STRNEH	ip,[a1,#6]

		ANDS	a2,a4,#&00F0
		AND	ip,a4,#&000F
		LDRNE	a2,[a3,a2,LSR #2]
		LDR	ip,[a3,ip,LSL #2]
		STRNEH	a2,[a1,#8]
		STRNEH	a2,[a1,#10]
		TST	a4,#&000F
		STRNEH	ip,[a1,#12]
		STRNEH	ip,[a1,#14]

		ANDS	a2,a4,#&F0000000
		AND	ip,a4,#&0F000000
		LDRNE	a2,[a3,a2,LSR #26]
		LDR	ip,[a3,ip,LSR #22]
		STRNEH	a2,[a1,#16]
		STRNEH	a2,[a1,#18]
		TST	a4,#&0F000000
		STRNEH	ip,[a1,#20]
		STRNEH	ip,[a1,#22]

		ANDS	a2,a4,#&00F00000
		AND	ip,a4,#&000F0000
		LDRNE	a2,[a3,a2,LSR #18]
		LDR	ip,[a3,ip,LSR #14]
		STRNEH	a2,[a1,#24]
		STRNEH	a2,[a1,#26]
		TST	a4,#&000F0000
		STRNEH	ip,[a1,#28]
		STRNEH	ip,[a1,#30]

		MOV	a1,#0
		MOV	pc,lr


TileFlip32_2	LDR	ip,=Pico
		ADD	ip,ip,#Pico_vram
		LDR	a4,[ip,a2,LSL #1]
		PLD	[ip,#64]

		TEQ	a4,#0
		MOVEQ	pc,lr

		ANDS	a2,a4,#&000F0000
		AND	ip,a4,#&00F00000
		LDRNE	a2,[a3,a2,LSR #14]
		LDR	ip,[a3,ip,LSR #18]
		STRNE	a2,[a1,#0]
		STRNE	a2,[a1,#4]
		TST	a4,#&00F00000
		STRNE	ip,[a1,#8]
		STRNE	ip,[a1,#12]

		ANDS	a2,a4,#&0F000000
		AND	ip,a4,#&F0000000
		LDRNE	a2,[a3,a2,LSR #22]
		LDR	ip,[a3,ip,LSR #26]
		STRNE	a2,[a1,#16]
		STRNE	a2,[a1,#20]
		TST	a4,#&F0000000
		STRNE	ip,[a1,#24]
		STRNE	ip,[a1,#28]

		ANDS	a2,a4,#&0000000F
		AND	ip,a4,#&000000F0
		LDRNE	a2,[a3,a2,LSL #2]
		LDR	ip,[a3,ip,LSR #2]
		STRNE	a2,[a1,#32]
		STRNE	a2,[a1,#36]
		TST	a4,#&000000F0
		STRNE	ip,[a1,#40]
		STRNE	ip,[a1,#44]

		ANDS	a2,a4,#&00000F00
		AND	ip,a4,#&0000F000
		LDRNE	a2,[a3,a2,LSR #6]
		LDR	ip,[a3,ip,LSR #10]
		STRNE	a2,[a1,#48]
		STRNE	a2,[a1,#52]
		TST	a4,#&0000F000
		STRNE	ip,[a1,#56]
		STRNE	ip,[a1,#60]

		MOV	a1,#0
		MOV	pc,lr


TileNorm32_2	LDR	ip,=Pico
		ADD	ip,ip,#Pico_vram
		LDR	a4,[ip,a2,LSL #1]
		PLD	[ip,#64]

		TEQ	a4,#0
		MOVEQ	pc,lr

		ANDS	a2,a4,#&F000
		AND	ip,a4,#&0F00
		LDRNE	a2,[a3,a2,LSR #10]
		LDR	ip,[a3,ip,LSR #6]
		STRNE	a2,[a1,#0]
		STRNE	a2,[a1,#4]
		TST	a4,#&0F00
		STRNE	ip,[a1,#8]
		STRNE	ip,[a1,#12]

		ANDS	a2,a4,#&00F0
		AND	ip,a4,#&000F
		LDRNE	a2,[a3,a2,LSR #2]
		LDR	ip,[a3,ip,LSL #2]
		STRNE	a2,[a1,#16]
		STRNE	a2,[a1,#20]
		TST	a4,#&000F
		STRNE	ip,[a1,#24]
		STRNE	ip,[a1,#28]

		ANDS	a2,a4,#&F0000000
		AND	ip,a4,#&0F000000
		LDRNE	a2,[a3,a2,LSR #26]
		LDR	ip,[a3,ip,LSR #22]
		STRNE	a2,[a1,#32]
		STRNE	a2,[a1,#36]
		TST	a4,#&0F000000
		STRNE	ip,[a1,#40]
		STRNE	ip,[a1,#44]

		ANDS	a2,a4,#&00F00000
		AND	ip,a4,#&000F0000
		LDRNE	a2,[a3,a2,LSR #18]
		LDR	ip,[a3,ip,LSR #14]
		STRNE	a2,[a1,#48]
		STRNE	a2,[a1,#52]
		TST	a4,#&000F0000
		STRNE	ip,[a1,#56]
		STRNE	ip,[a1,#60]

		MOV	a1,#0
		MOV	pc,lr


		END
